Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - receivers LVDS 0/1 UQFN 10

VCC

NC GND

VDD

SN65LVDS4 (Receiver)

LVDS4 in QFN Package

(BOTTOM VIEW)

BGND

NC NC

VCC

NCGND

VDD

SN65LVDS4 (Receiver)

LVDS4 in QFN Package

(TOP VIEW)

B GND

NCNC

SN65LVDS4

www.ti.com

SLLSE15 –JULY 2011

1.8-V HIGH-SPEED DIFFERENTIAL LINE RECEIVER

Check for Samples: SN65LVDS4

FEATURES

DESCRIPTION

The SN65LVDS4 is a single, low-voltage, differential

• Designed for Signaling Rates up to:

line receiver in a small-outline QFN package.

– 500-Mbps Receiver

The signaling rate of a line is the number of voltage transitions that

are made per second expressed in the units bps (bits per second)

• Operates From a 1.8-V or 2.5-V Core Supply

• Available in 1.5-mm × 2-mm QFN Package

• Bus-Terminal ESD Exceeds 2 kV (HBM)

• Low-Voltage Differential Signaling With Typical

Output Voltages of 350 mV Into a 100-Ω Load

• Propagation Delay Times

– 2.1 ns Typical Receiver

• Power Dissipation at 250 MHz

– 40 mW Typical

• Requires External Failsafe

• Differential Input Voltage Threshold Less Than

50 mV

Table 1. Pin Description Table

• Can Provide Output Voltage Logic Level (3.3-V

LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based

I/O DESCRIPTION

on External VDD Pin, Thus Eliminating

NAME NO.

External Level Translation

A 2 I LVDS input, positive

B 3 I LVDS input, negative

APPLICATIONS

GND 1, 7 – Ground

• Clock Distribution

NC 4, 6, 9 – No connect

• Wireless Base Stations

R 8 O 1.8/2.5 LVCMOS/3.3 LVTTL output

• Newtwork Routers

VCC 5 – Core supply voltage

VDD 10 – Output drive voltage

AVAILABLE OPTIONS

PART NUMBER INTEGRATED TERMINATION PACKAGE PACKAGE MARKING

SN65LVDS4RSE No QFN QXB

SPACER

The SN65LVDS4 is characterized for operation from –40°C to 85°C.

Table 2. FUNCTION TABLE

INPUTS OUTPUT

(1)

= V

– V

≥ 50 mV H

≤ –50 mV L

(1) H = high level, L = low level, ? = indeterminate

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com 1.8-V HIGH-SPEED DIFFERENTIAL LINE RECEIVER Check for Samples: SN65LVDS4 FEATURES DESCRIPTION • The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline QFN package. 1 Designed for Signaling Rates up to: – 500-Mbps Receiver The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second) • • • • • • • • • Operates From a 1.8-V or 2.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VDD VDD VCC VCC 5Ω R A B ESD ESD ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Values PARAMETER (2) MIN MAX Units –0.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com THERMAL INFORMATION SN65LVDS4 THERMAL METRIC (1) RSE UNIT 10 PINS Junction-to-ambient thermal resistance (2) θJA (3) 171.2 °C/W θJCtop Junction-to-case (top) thermal resistance 60.7 °C/W θJB Junction-to-board thermal resistance (4) 71.4 °C/W ψJT Junction-to-top characterization parameter (5) 0.8 °C/W ψJB Junction-to-board characterization parameter (6) 64.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER VITH+ Positive-going differential input voltage threshold VITH– Negative-going differential input voltage threshold VOH High-level output voltage VOL Low-level output voltage MIN (1) TEST CONDITIONS TYP (2) MAX 50 See Figure 1, VCC1.8 , VCC2.5 –50 VDD = 3.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX tPLH Propagation delay time, low-to-high-level output 2.5 tPHL Propagation delay time, high-to-low-level output 2.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION IIA V IA )V A IO IB 2 VIA IIB VID B VIC R VO VIB Figure 1. Receiver Voltage and Current Definitions 1000 Ω 100 Ω 1000 Ω VIC + -- 100 Ω † VID 10 pF, 2 Places VO 10 pF † Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. VIT+ 0V VID –50 mV VO 50 mV VID 0V VIT– VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V −0.4 V tPHL VO tPLH VOH 80% 0.5 VCC 20% VOL tf A. tf All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 3.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.5 1.25 1 Low-Level Output Voltage (V) High-Level Output Voltage (V) 3 2.5 2 1.5 1 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 0.5 0 VCC = 1.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted RISE TIME vs CAPACITIVE LOAD FALL TIME vs CAPACITIVE LOAD 800 800 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 700 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 700 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted PULSE SKEW vs TEMPERATURE PULSE SKEW vs COMMON-MODE VOLTAGE 180 160 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 140 120 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V 140 Pulse Skew (ps) Pulse Skew (ps) VDD = 1.8 V VDD = 2.5 V VDD = 3.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted PROPAGATION DELAY, LOW-TO-HIGH vs DIFFERENTIAL INPUT VOLTAGE PROPAGATION DELAY, HIGH-TO-LOW vs COMMON-MODE VOLTAGE 3.3 VCC = 1.8 V, VCC = 1.8 V, VCC = 1.8 V, VCC = 2.5 V, VCC = 2.5 V, 2.6 2.5 VDD = 1.8 V VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com APPLICATION INFORMATION VINMAX VCC VDD VIA R VICM VIB |VID| = |VIA –VIB| VCC2.5 VIA (V) 1.25 1.2 2.2 2.25 0.05 0 VCC1.8 VCC2.5 (Note: Worst-Case VCC = 2.5 – 10% = 2.25 V) VIB (V) 1.2 1.25 2.25 2.2 0 0.05 VID (mV) 50 50 50 50 50 50 VICM (V) 1.225 1.225 2.225 2.225 0.025 0.025 VIA (V) 1.5 0.9 1.65 2.25 0.6 0 VCC1.8 (Note: Worst-Case VCC = 1.8 – 10% =1.62 V) VIA (V) 1.25 1.2 1.57 1.62 0.05 0 VIB (V) 1.2 1.25 1.62 1.57 0 0.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com FAILSAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range.
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SN65LVDS4 SLLSE15 – JULY 2011 www.ti.com Parallel Terminated 100 Ω 100 Ω Point to Point 100 Ω Multidrop 100 Ω Figure 22.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 9-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS4RSER UQFN RSE 10 3000 180.0 8.4 1.68 2.13 0.76 4.0 8.0 Q1 SN65LVDS4RSET UQFN RSE 10 250 180.0 8.4 1.68 2.13 0.76 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS4RSER UQFN RSE 10 3000 202.0 201.0 28.0 SN65LVDS4RSET UQFN RSE 10 250 202.0 201.0 28.
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