Datasheet

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
|V
OD
| Differential output voltage magnitude
R
L
= 100 Ω
247 340 454
∆|V
OD
|
Change in differential output voltage
magnitude between logic states
R
L
=
100
Ω
,,
See Figure 1 and Figure 2
–50 50
mV
V
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 V
∆V
OC(SS)
Change in steady-state common-mode output
voltage between logic states
See Figure 3
–50 50 mV
V
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mV
’LVDS387
Enabled,
85 95
’LVDS389
Enabled
,
R
L
= 100 Ω,
50 70
I
CC
Su
pp
ly current
’LVDS391
V
IN
= 0.8 V or 2 V
20 26
mA
I
CC
Supply
current
’LVDS387
Di bl d
0.5 1.5
mA
’LVDS389
Disabled,
V
IN
=0VorV
CC
0.5 1.5
’LVDS391
V
IN
=
0
V
or
V
CC
0.5 1.3
I
IH
High-level input current V
IH
= 2 V 3 20 µA
I
IL
Low-level input current V
IL
= 0.8 V 2 10 µA
I
OS
Short circuit out
p
ut current
V
OY
or V
OZ
= 0 V ±24 mA
I
OS
Short
-
circuit
output
current
V
OD
= 0 V ±12 mA
I
OZ
High-impedance output current V
O
= 0 V or V
CC
±1 µA
I
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 2.4 V ±1 µA
C
IN
Input capacitance V
I
= 0.4 sin (4E6πt) + 0.5 V 5 pF
C
O
Output capacitance
V
I
= 0.4 sin (4E6πt) + 0.5 V,
Disabled
9.4 pF
†
All typical values are at 25°C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns
t
PHL
Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns
t
r
Differential output signal rise time
R
L
= 100 Ω
0.4 0.8 1 ns
t
f
Differential output signal fall time
R
L
=
100
Ω
,
C
L
= 10 pF,
0.4 0.8 1 ns
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|)
L
See Figure 4
150 500 ps
t
sk(o)
Output skew
‡
80 150 ps
t
sk(pp)
Part-to-part skew
§
1.5 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output 6.4 15 ns
t
PZL
Propagation delay time, high-impedance-to-low-level output
See Figure 5
5.9 15 ns
t
PHZ
Propagation delay time, high-level-to-high-impedance output
See
Figure
5
3.5 15 ns
t
PLZ
Propagation delay time, low-level-to-high-impedance output 4.5 15 ns
†
All typical values are at 25°C and with a 3.3-V supply.
‡
t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all drivers of a single device with all of their inputs connected together.
§
t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.