Datasheet

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Host
Controller
TX Clock
SN65LVDS387 or 389
Target
Controller
Target
LVDS Receiver(s)
Indicates twisting of the
conductors.
T
T
T
T
T
Indicates the line termination
circuit.
Host
Balanced Interconnect
Power Power
DB0
DB1
DB2
DBn–3
T
T
T
T
DBn–2
DBn–1
DBn
RX Clock
DB0
DB1
DB2
DBn–3
DBn–2
DBn–1
DBn
Figure 14. Typical Application Schematic
Signaling Rate vs Distance
The ultimate data transfer rate over a given cable or trace length involves many variables. Starting with the
capabilities of this LVDS driver to reproduce a data pulse as short as 1.6 ns (a 630 Mbps signaling rate) with
less than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily
reduce the timing margin at the receiving end of the data link.
The timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from
numerous sources. The characteristics of a particular transmission media can be quantified by using an
eyepattern measurement such as shown in Figure 12, which shows about 340 ps of jitter or 20% of the data
pulse width.