Datasheet

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V
ID
V
O
10 pF10 pF 10 pF
100 Ω
†
1000 Ω
1000 Ω
100 Ω
V
IC
V
2
+
+
V
1
+
–
–
–
V
ITH1
V
ID
0 V
–100 mV
100 mV
0 V
V
ITH2
V
O
V
ID
V
O
SN65LVDS348 , SN65LVDT348
SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A. Remove for testing LVDT device.
B. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns.
C. Fixture capacitance ±20%.
D. Resistors are metal film, 1% tolerance, and surface mount
Figure 2. V
ITH1
and V
ITH2
, Input Voltage Threshold Test Circuit and Definitions
Table 1. Receiver Minimum and Maximum Failsafe Input Voltage
FAILSAFE THRESHOLD TEST VOLTAGES
APPLIED VOLTAGES
(1)
RESULTANT INPUTS
Output
V
IA
(mV) V
IB
(mV) V
ID
(mV) V
IC
(mV)
-4000 -3900 -100 -3950 L
-4000 -3968 -32 -3984 H
4900 5000 -100 4950 L
4968 5000 -32 4984 H
(1) Voltage applied for greater than 1.5 µs.
8
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