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Rt
300 kΩ 300 kΩ
V
CC
V
IT
≈ 2.3 V
A
B
Y
1B
1A
1Y
G
2Y
2A
2B
GND
V
CC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100 Ω
100 Ω
100 Ω
(see Note B)
100 Ω
V
CC
See Note C
≈3.6 V
0.1 µF
(see Note A)
1N645
(two places)
0.01 µF
5 V
SN55LVDS32 , SN65LVDS32
SN65LVDS3486 , SN65LVDS9637
SLLS262Q – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could
be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS
receiver pulls each line of the signal pair to near V
CC
through 300-k Ω resistors (see Figure 18 ). The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
Figure 18. Open-Circuit Fail-Safe of LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as
it is connected as shown in Figure 18 . Other termination circuits may allow a dc current to ground that could
defeat the pullup currents from the receiver and the fail-safe feature.
A. Place a 0.1- μ F Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V
CC
and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
± 10%.
C. Unused enable inputs should be tied to V
CC
or GND, as appropriate.
Figure 19. Operation With 5-V Supply
18
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