Datasheet

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APPLICATION INFORMATION
1/4 ’LVDS31
’LVDS32
500 Ω
500 Ω
20 kΩ
20 kΩ
3.3 V
500 Ω
500 Ω
20 kΩ
20 kΩ
3.3 V
7 kΩ7 kΩ
10 kΩ
3.3 kΩ
Twisted-Pair B Only
Strb/Data_TX
Strb/Data_Enable
Data/Strobe
1 Arb_RX
2 Arb_RX
Port_Status
TpBias on
Twisted-Pair A
55 Ω
55 Ω
5 kΩ
VG on
Twisted-Pair B
TP
TP
3.3 V
FAIL-SAFE
SN55LVDS32 , SN65LVDS32
SN65LVDS3486 , SN65LVDS9637
SLLS262Q – JULY 1997 – REVISED JULY 2007
A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown but recommended.
C. V
CC
is 3 V to 3.6 V.
D. The differential output voltage of the 'LVDS31 can exceed that allowed by IEEE1394.
Figure 17. 100-Mbps IEEE 1394 Transceiver
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and100 mV if
it is within its recommended input common-mode voltage range. However, TI LVDS receivers handle the
open-input circuit situation differently.
17
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