Datasheet

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_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
B
R
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
R3 R3
V
CC
I
CC
5 Meters
of CAT-5
R1 R1
V
EE
R2
V
CC
I
CC
R3 = 240 Ω
R1 = 50 Ω
R2 = 50 Ω
V
B
V
B
LVDSLV/PECL
SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 13. Receiver With Terminated Failsafe
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a
design option, designers have been able to take advantage of LVDS by implementing a small resistor divider
network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode
LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the
termination bias voltage required for ECL termination (V
CC
– 2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received
by TI's wide common-mode receiver and the resulting eye pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω . The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
15
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