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1A
1Y
1Z
G
2Z
2Y
2A
GND
V
CC
4A
4Y
4Z
G
3Z
3Y
3A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Z
O
= 100 Ω
Z
O
= 100 Ω
Z
O
= 100 Ω
Z
O
= 100 Ω
≈3.6 V
0.1 µF
(see Note A)
V
CC
See Note B
1N645
(2 places)
0.01 µF
5 V
COLD SPARING
RELATED INFORMATION
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
A. Place a 0.1- μ F Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V
CC
and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to V
CC
or GND, as appropriate.
Figure 11. Operation With 5-V Supply
Systems using cold sparing have a redundant device electrically connected without power supplied. To support
this configuration, the spare must present a high-input impedance to the system so that it does not draw
appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
When the device is powered off, V
CC
must be clamped to ground and the I/O voltages applied must be within the
specified recommended operating conditions.
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
• Low-Voltage Differential Signaling Design Notes (SLLA014 )
• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038 )
• Reducing EMI With LVDS (SLLA030 )
• Slew Rate Control of LVDS Circuits (SLLA034 )
• Using an LVDS Receiver With RS-422 Data (SLLA031 )
• Evaluating the LVDS EVM (SLLA033 )
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