Datasheet

CLK+
D0+/-
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 11 0 0 0 0 0
0 0
1
VS (Frame Valid)
HS (Line Valid)
A B C B D E
Last Visible Line
A - Time between VS and HS rising edge:
B - Number of pixel in active line:
C - Horizonal line blanking:
D - Time between VS and HS falling edge:
E - Time between VS falling and VS rising edge:
0 t£
A
0 t
8x1/f t
0 t
if MODE = high or t = 0: 8x1/f t
if MODE = low or t > 0: 12x1/f t
£
£
£
£
£
B
DCLK C
D
D DCLK E
D DCLK E
HS
(LineValid)
DCLK
D[0:7]
Blanking
ValidImageData Blanking
P0 P1 P2 P3 P4 P(n-1) Pn
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012 www.ti.com
FUNCTIONAL DESCRIPTION
Parallel Input Port Timing Information
The parallel input data must comply with the following signal timing:
Figure 1. Parallel Input Timing Diagram
The relationship between frame sync and line sync shall be the following:
Figure 2. VS and HS Timing Diagram
MIPI CSI-1 / CCP2-Class 0 Interface
When MODE is held low, the SN65LVDS315 provides a MIPI CSI-1 compliant serial output. The output data on
DOUT is set on each falling edge of the differential clock signal, CLK. The CSI-1/CCP2 receiver should latch the
data in on the rising CLK edge. The clock signal is free running (and not gated as optional in the CCP2 spec).
The data format is bytewise (8-bit boundary) with the least significant bit (LSB) sent first. When nothing is being
transferred (e.g. during blanking), DOUT remains high, except during power shutdown.
Figure 3. Data and Clock Output in CSI-1/CCP2
Camera Mode Class-0 Transferring a Data Sequence of 0xFF011223h
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