Datasheet

SN65LVDS315
www.ti.com SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
Table 1. Pin Description QFN Package
PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL
1 GNDD 7 TXEN 13 D3 19 D7
2 DOUT– 8 MODE 14 D4 20 VS
3 DOUT+ 9 VDDA 15 D5 21 HS
4 CLK– 10 D0 16 DCLK 22 VDDIO
5 CLK+ 11 D1 17 GNDD 23 VDDD
6 GNDA 12 D2 18 D6 24 FSEL
Table 2. PIN FUNCTIONS
PIN
DESCRIPTION
NAME TYPE
SubLVDS data link CSI-1 compliant (active during normal operation; high-impedance during
DOUT+, DOUT–
power down or standby) DOUT is valid on the rising edge of CLK+.
SubLVDS out
CLK+, CLK– SubLVDS clock output (CSI-1 Mode 0 compliant)
Data inputs (8) for pixel data;
These inputs are sampled on the falling DCLK edge;
D0–D7
inputs incorporate bus hold
Note: D[7:0] states are latched into the SN65LVDS315 on the falling DCLK input edge
Vertical Sync (also called frame sync);
VS Data input (high active). This input is sampled on every falling DCLK edge
Input incorporates bus hold
CMOS in
(1)
Horizontal Sync (also called line sync);
HS Data input (high active). This input is sampled on every falling DCLK edge
Input incorporates bus hold
Data input Clock;
DCLK represents the camera pixel clock. All 8 pixel bits as well as VS and HS are latched into
DCLK
the device on the falling edge of DCLK (falling edge clocking)
Input incorporates bus hold
Disables the subLVDS Drivers and turns off the PLL putting device in Shutdown mode
1 – Transmitter enabled
0 – Transmitter disabled (shutdown)
TXEN
Note: TXEN input incorporates glitch-suppression logic to avoid device malfunction on short
input spikes. It is necessary to pull TXEN high for longer than 10 μs to enable the transmitter. It
is necessary to pull the TXEN input low for longer than 10 μs to disable the transmitter. At
power up, the transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0.
Do not leave TXEN floating.
CMOS in
(2)
Frequency Select
FSEL=0: DCLK input frequencies from 3.5 MHz to 13 MHz are supported
FSEL
FSEL=1: DCLK input frequencies from 7.0 MHz to 27 MHz are supported
Do not leave FSEL floating.
The mode pin enables line counting to generate proper EOF signalling in case VS and HS do
not reset during the same DCLK cycle (0-line counter disable; 1-counter enabled). The impact
MODE of the MODE pin setting is described in detail in the VS and HS Timing to Generate the Correct
Control Signals section. If you are unsure about the proper setting of the MODE input, it is
recommended to set MODE=high. Do not leave the MODE input floating.
VDDIO IO Supply Voltage for inputs D[0:7], HS, VS, and DCLK, (1.8 V up to 3.3 V)
VDDD Digital supply voltage (1.8 V only)
GNDD Power Supply
(3)
Supply Ground for VDDIO and VDDD
VDDA PLL and SubLVDS I/O supply voltage (1.8 V only)
GNDA PLL and SubLVDS Ground
(1) These inputs are referenced to the VDDIO supply rail and support a voltage range of 1.65 V to 3.6 V
(2) These inputs can tolerate an input voltage up to 3.6 V while the actual input threshold from logic low to logic high is at 0.9 V nominal;
This allows driving these inputs from a 1.8 V or 3.3 V GPIO independent of the camera supply voltage.
(3) In a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly
to this plane.
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