Datasheet

SN65LVDS315
www.ti.com SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
REVISION HISTORY
Changes from Original (December 2007) to Revision A Page
• Changed the document From: Product Preview To: Production .......................................................................................... 1
Changes from Revision A (March 2008) to Revision B Page
• Changed the Absoulute Maximum Ratings table - Voltage range at any input terminal value From: –0.5 to 2.175 To:
–0.5 to VDDIO + 0.5V ......................................................................................................................................................... 13
Changes from Revision B (November 2008) to Revision C Page
• Changed Figure 2: Note E - From: "Time between HS falling and HS rising edge" To: "Time between VS falling and
VS rising edge ...................................................................................................................................................................... 4
• Changed the Acquire Mode (PLL Approaches Lock) section. From: "HS low-to-high" To: VS low-to-high and From
"MODE is set low"; To: "MODE is set high" ........................................................................................................................ 11
• Changed text in the VGA CAMERA APPLICATION section From: The pixel clock rate is 11 MHz, assuming ≉10%
blanking overhead. To: The pixel clock rate is 11 MHz, assuming ≈20% blanking overhead ........................................... 25
Changes from Revision C (June 2001) to Revision D Page
• Changed Feature From: Pixel Clock Range 3.5–26 MHz To: Pixel Clock Range 3.5–27 MHz ........................................... 1
• Chnaged the pin function for FSEL From: FSEL=1: DCLK input frequencies from 7.0 MHz to 26 MHz are supported
To: FSEL=1: DCLK input frequencies from 7.0 MHz to 27 MHz are supported ................................................................... 3
• Changed Data clock frequency for FSEL = 1 in the ROC table From: MAX = 26 MHz To: MAX = 27 MHz ..................... 14
• Changed the ROC table section MODE, TXEN, FSEL To: MODE, TXEN ........................................................................ 14
• Added section FSEL to the ROC table ............................................................................................................................... 14
• Changed the TYPICAL APPLICATION FREQUENCIES section. From: The SN65LVDS315 in display mode
supports pixel clock frequencies from 7 MHz to 26 MHz To: The SN65LVDS315 in display mode supports pixel
clock frequencies from 7 MHz to 27 MHz ........................................................................................................................... 25
Changes from Revision D (February 2012) to Revision E Page
• Added test to the DESCRIPTION: "A certain differential termination circuit must be implemented..." ................................ 1
• Added the RECEIVER TERMINATION REQUIREMENT section ...................................................................................... 24
Changes from Revision E (August 2012) to Revision F Page
• deleted ΔV
OCM(SS)
and V
OCM(PP)
From the OUTPUT ELECTRICAL CHARACTERISTICS ................................................. 15
• Changed the RECEIVER TERMINATION REQUIREMENT section .................................................................................. 24
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