Datasheet

EntireFrame
Visiblearea
Visiblearea = 640 column
Visiblearea
=480 lines
Vertical
blanking
horizontal
blanking
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012 www.ti.com
8-Bit Camera Application
Table 9. Typical Application Data Rates and Serial Lane Usage
FRAME
DISPLAY SCREEN VISIBLE CONTROL DCLK PIXEL CLOCK DATA RATE ON D0
REFRESH f(CLK)
RESOLUTION PIXEL COUNT OVERHEAD FREQUENCY [MHz] WITH LS=0
RATE
640x480 (VGA) 307,200 14% 10 Hz 3.5 MHz 28 Mbps 28 MHz
640x480 (VGA) 307,200 2% 15 Hz 4.7 MHz 38 Mbps 38 MHz
640x480 (VGA) 307,200 10% 30 Hz 10.1 MHz 81 Mbps 81 MHz
3 Mpixel 3,000,000 10% 7 Hz 23.1 MHz 185 Mbps 185 MHz
4 Mpixel 4,000,000 10% 5 Hz 22.0 MHz 176 Mbps 176 MHz
5 Mpixel 5,000,000 10% 4 Hz 22.0 MHz 176 Mbps 176 MHz
6 Mpixel 6,000,000 10% 3 Hz 19.8 MHz 158 Mbps 158 MHz
8 Mpixel 8,000,000 10% 2 Hz 17.6 MHz 141 Mbps 141 MHz
10 Mpixel 10,000,000 10% 2 Hz 22.0 MHz 176 Mbps 176 MHz
12 Mpixel 12,000,000 10% 2 Hz 25.1 MHz 201 Mbps 201 MHz
Calculation Example: VGA Camera Sensor
The following calculation shows an example for a VGA camera with following parameter:
display resolution: 640 x 480
frame refresh rate: 30 fps
vertical visible pixel: 480 lines
vertical blanking: 10 lines
horizontal visible pixel: 640 columns
horizontal blanking: 5 columns
Calculation of the total number of pixel and Blanking overhead:
visible area pixel count: 640 x 480 = 307,200 pixel
total frame pixel count: (640+5) x (480+10) = 316,050 pixel
blanking overhead: (316,050–307,200) div 307,200 = 2.8%
The application requires following serial link parameters:
pixel clk frequency: f
DCLK
= 316.050 x 30 Hz = 9.5 MHz
DOUT serial data rate: dR = f
DCLK
x8 = 76 Mbps
CLK output clock rate: f
CLK
= f(dR) = 76 MHz
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