Datasheet

SN65LVDS315
www.ti.com SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
Jitter Performance
The jitter performance of the SN65LVDS315 is tested using a pattern that stresses the interconnect, particularly
to test for ISI. The test pattern uses very long run lengths of consecutive bits. The pattern incorporates very high
and low data rates, and maximizes switching noise. The pattern is self-repeating for the duration of the test.
Table 8. Jitter Test Pattern
TEST PATTERN
WORD
D[7:0] VS HS
1 0x00 1 1
2 0x00 1 1
3 0x00 1 1
4 0x01 1 1
5 0x03 1 1
6 0x07 1 1
7 0x18 1 1
8 0xE7 1 1
9 0x35 1 1
10 0x02 1 1
11 0x54 1 1
12 0xA5 1 1
13 0xAD 1 1
14 0x55 1 1
15 0xA6 1 1
16 0xA6 1 1
17 0x55 1 1
18 0x55 1 1
19 0xAA 1 1
20 0x52 1 1
21 0x5A 1 1
22 0xAB 1 1
23 0xFD 1 1
24 0xCA 1 1
25 0x18 1 1
26 0xE7 1 1
27 0xF8 1 1
28 0xFC 1 1
29 0xFE 1 1
30 0xFF 1 1
31 0xFF 1 1
32 0xFF 1 1
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links :SN65LVDS315