Datasheet

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7
8
9
10
11
12
131415161718
19
20
21
22
23
24
D7
VS
HS
VDDIO
VDDD
FSEL
GNDD
DOUT-
DOUT+
CLK-
CLK+
GNDA
TXEN
MODE
VDDA
D0
D1
D2
D3 D4 D5 DCLK GNDD D6
PacketEngine:
PacketValidation
8-BitParalleltoSerial
SubLVDS
SubLVDS
Counter
LineCount
PLL
x8
LowFrequency
Detector
Glitch
Supression
Standby,Shutdown,andStartupController
DOUT+
DOUT-
CLK+
CLK-
D[0:7]
HS
VS
MODE
DCLK
TXEN
8
8
Load
Reset
++
ForceEOF
&
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
24-PIN QFN 0.5MM PITCH (RGE)
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