Datasheet

t
F
t
R
0V
20%
80%
150mV(nom)
-150mV(nom)
V
OD
CLK+
t
CLK+
Bit(n-1) Bitn
CLK-
DOUT+/-
t
s(DOUT)
t
h(DOUT)
t
DS
t
DH
D[0:7],VS,HS
DCLK
t
F
80%V
OH
20%V
OL
80%V
OH
20%V
OL
SN65LVDS315
www.ti.com SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
Figure 10. Input signal Setup and Hold Time Definition t
DS
and t
DH
Figure 11. Output signal Setup and Hold Time Definition t
s(DOUT)
and t
h(DOUT)
Figure 12. Rise and Fall Time Definition
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