Datasheet
Input Output
CLK+,
DOUT+
I
O
D[0:7], VS,
HS, FSEL,
TXEN, MODE
I
I
V
O-
V
I
CLK-,
DOUT-
I
O
V
O+
V
OD
V
OCM
(V +V )/2
O+ O-
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
20%-to-80% differential output signal rise f
DCLK
=3.5 MHz, See Figure 12 and
t
r
360 460 730 ps
time Figure 13
20%-to-80% differential output signal fall f
DCLK
=3.5 MHz, See Figure 12 and
t
f
360 460 730 ps
time Figure 13
FSEL = 0, f
DCLK
= 13 MHz 3.327 4.2
Setup time DOUT valid before CLK+
t
s(DOUT)
ns
rising edge
FSEL = 1, f
DCLK
= 26 MHz 1.163 1.8
See
Figure 11
FSEL = 0, f
DCLK
= 13 MHz 4.627 5.4
Hold time DOUT valid before CLK+
t
h(DOUT)
ns
ringing edge
FSEL = 1, f
DCLK
= 26 MHz 2.463 3.0
TXEN at V
DDD
, V
IH
= V
DDD
, V
IL
=GND,
Propagation delay time, input to serial
t
pd(L)
4.5/f
DCLK
4.7/f
DCLK
5.5/f
DCLK
output (data latency)
R
L
= 100 Ω, See Figure 14
t
H
x f
CLKO
Output CLK duty cycle 0.45 0.50 0.55
TXEN glitch suppression pulse width
(2)
V
IH
= V
DDD
, V
IL
=GND, TXEN toggles
t
GS
3.8 10 μs
between V
IL
and V
IH
, See Figure 16
Enable time from power down (↑TXEN) MODE at V
DD
; time from TXEDN pulled
100μs +
t
pwnup
high to CLK and DOUT outputs enabled 100 μs
2×VS↑
and transmit valid data; See Figure 16
Disable time from active mode (↓TXEN) TXEN is pulled low during transmit mode;
time measurement until output becomes
t
pwrdn
11 μs
disabled and PLL is shutdown; See
Figure 16
Enable time from standby (↑↓DCLK) TXEN and MODE at V
DD
; device in
standby; time measurement from DCLK
100μs +
t
wakup
starts switching to CLK and DOUT 100 μs
2×VS↑
enabled and transmit valid data; See
Figure 17
Disable time from standby (DCLK TXEN at V
DD
; device in transmitting; time
stopping) measurement from DCLK input signal
t
sleep
stops starts until CLK + DOUT outputs <8/f
DCLK
100 μs
becomes disabled and PLL is shutdown,
See Figure 17
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. t
GS
is the duration of either a high-to-low or low-
to-high transition that is suppressed.
MEASUREMENT INFORMATION
Figure 9. I/O Voltage and Current Definition
16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links :SN65LVDS315