Datasheet
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
www.ti.com
THERMAL CHARACTERISTICS
PARAMETER TEST CONDITIONS VALUE UNIT
V
DDx
= 1.8 V, T
A
= 25°C f
DCLK
= 3.5 MHz 10.8 mW
Typical f
DCLK
= 11 MHz 17.7 mW
f
DCLK
= 26 MHz 21.2 mW
P
D
Device power dissipation
V
DDx
= 1.95 V, T
A
= –40°C f
DCLK
= 3.5 MHz 15.7 mW
Maximum
f
DCLK
= 26 MHz 26.0 mW
RECOMMENDED OPERATING CONDITIONS
(1)
MIN NOM MAX UNIT
VDDIO 1.65 3.6
VDDD Supply voltage 1.65 1.8 1.95 V
VDDA 1.65 1.8 1.95
f(V
DDn(PP)
) = 1 Hz to 2 GHz (test set-up see
V
DDn(PP)
Supply voltage noise magnitude 100 mV
Figure 15)
FSEL = 0, See Figure 1, Figure 2, Figure 3 3.5 13
MHz
f
DCLK
Data clock frequency FSEL = 1, See Figure 1, Figure 2, Figure 3 7 27
Standby mode
(2)
500 kHz
t
H
x f
DCLK
DCLK Input duty cycle 0.35 0.65
T
A
Operating free-air temperature –40 85 °C
t
jit(per)DCLK
DCLK RMS period jitter
(3)
5 ps-rms
t
jit(TJ)DCLK
DCLK total jitter
(4)
Measured on DCLK input 0.05/f
DCLK
s
t
jit(CC)DCLK
DCLK peak cycle to cycle jitter
(5)
0.02/f
DCLK
s
MODE = V
IH
; count the number of HS↓
Icount Number of active video lines
(6)
1 2046
transitions within one frame
UI
t
hblank
Horizontal blanking time 4
(1/DCLK)
UI
t
vblank
Vertical blanking time 8
(1/DCLK)
DCLK, D[0:1], VS, HS
V
IH
High-level input voltage See Figure 9 0.7×V
DDIO
V
DDIO
V
V
IL
Low-level input voltage See Figure 9 0 0.3×V
DDIO
V
t
DS
Data set up time prior to ↑↓ DCLK See Figure 10 2.0 ns
t
DH
Data hold time after ↑↓ DCLK See Figure 10 2.0 ns
MODE, TXEN
V
IH
High-level input voltage See Figure 9 0.7×V
DDA
3.6 V
V
IL
Low-level input voltage See Figure 9 0 0.3×V
DDA
V
FSEL
V
IH
High-level input voltage See Figure 9 0.7×V
DDD
3.6 V
V
IL
Low-level input voltage See Figure 9 0 0.3×V
DDD
V
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) DCLK input frequencies lower than 500 kHz will force the SN65LVDS315 into standby mode. Input frequencies between 500 kHz and 3
MHz might activate the SN65LVDS315. Input frequencies beyond 3MHz will activate the SN65LVDS315.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Total jitter reflects the maximum jitter amplitude observed over a time period of 10
12
data bits. It is often derived by adding all
deterministic jitter components (ps peak-to-peak values) and the geometric sum of all random components (ps-rms values × 14.069 for
10–12 bit error rate)
(5) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles over a random sample of 1,000 adjacent cycle
pairs.
(6) For a VGA resolution of 640x480, lcount would be 480
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