Datasheet

SN65LVDS315
www.ti.com SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012
Following data formats are not supported by the SN65LVDS315:
– RGB 444 image data – Raw Bayer 10-bit image data
– Raw Bayer 6-bit image data – Raw Bayer 12-bit image data
– Raw Bayer 7-bit image data – JPEG 8-bit data
POWERDOWN MODES
The SN65LVDS315 transmitter has two power-down modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS315 enters shutdown mode when the TXEN terminal is asserted low. This turns off all transmitter
circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high
impedance. Current consumption in shutdown mode is nearly zero.
Standby Mode
The SN65LVDS315 enters the standby mode if TXEN is high and the DCLK input signal frequency is less than
500 kHz. All circuitry except the DCLK input monitor is shut down, and all outputs enter the high-impedance
state. The current consumption in standby mode is low. When the DCLK input signal is completely stopped, the
IDD current consumption is minimized.
NOTE
Leaving the TXEN, FSEL or MODE input floating (left open) allows leakage currents to
flow from V
DD
to GND. To prevent excessive leakage current, a CMOS gate must be kept
at a valid logic level, either high (above V
IH
min) or low (below V
IL
min). This can be
achieved by applying an external voltage or ground to these inputs. Inputs Dx, VS, HS,
and DCLK incorporate bus hold, and can be left floating or tied high or low. Switching
inputs also causes increased leakage currents. Only if no input signal is switching will the
I
DD
current be at its minimum.
ACTIVE MODES
When TXEN is high and the DCLK input clock frequency is higher than 3 MHz, the SN65LVDS315 enters the
active mode. Current consumption in the active mode depends on operating frequency and the number of data
transitions in the data payload.
Acquire Mode (PLL Approaches Lock)
The PLL is enabled and attempts to lock to the input clock. All outputs remain in the high-impedance state. First,
the PLL monitor waits until it detects stable PLL operation. If MODE is set low, the digital core will wait for one
VS low-to-high transition (new frame start) before the device switches from the acquire mode to the transmit
mode. This ensures that the outputs turn on when a new image frame is transmitted by the camera sensor. If
MODE is set high, the digital core will wait for two (instead of one) VS low-to-high transitions before the device
switches from the acquire mode to the transmit mode. This not only ensures that the device waits for a new
camera frame, but also allows the internal SN65LVDS315 counter to be initiated with the proper line count. For
proper device operation, the pixel-clock frequency (f
DCLK
) must fall within the valid f
DCLK
range specified under
recommended operating conditions. If the pixel clock frequency is higher than 3 MHz but lower than f
DCLK
(min),
the SN65LVDS315 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the
pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or
may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL
deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK and DOUT terminals output
CSI-1 compliant serial data.
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