Datasheet

PowerUp
TXEN=0
TXENLow
for>10 sm
TXENHigh
for>10 sm
ShutDown
Mode
Standby
Mode
PowerUp
TXEN=1
DCLKInputInactive
DCLKStops
orLost
DCLK Active
DCLKStops
orLost
TXENLow
for>10 sm
PowerUp
TXEN=1
DCLK Active
TXENLow
for>10 sm
Transmit
Mode
Acquire
Mode
PLL AchievedLock;
ifMODE=High:
Waitfor2FrameCounts
(socounterisinitiatedproperly)
SN65LVDS315
SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012 www.ti.com
STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN65LVDS315 switches between the power saving and active modes in the following way:
Figure 8. Status Detect and Operating Modes Flow Diagram
Table 4. Status Detect and Operating Modes Descriptions
MODE CHARACTERISTICS CONDITIONS
Shutdown Mode Least amount of power consumption (most circuitry turned off); TXEN is low for longer than 10 μs
(1) (2)
All outputs high impedance.
Standby Mode Low power consumption (only clock activity circuit active; PLL TXEN is high for longer than 10 μs; DCLK input signal
is disabled to conserve power); all outputs are high impedance. is missing or inactive.
(2)
Acquire Mode PLL tries to achieve lock; if MODE is high, initiate line counter TXEN is high; DCLK input monitor detected input
(to place EOF at proper position); All outputs are high activity.
impedance.
Transmit Mode Data transfer (normal operation); transmitter serializes data TXEN is high and PLL is locked to the incoming clock.
and transmits data on serial output.
(1) In Shutdown Mode, all SN65LVDS315 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
(2) Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs without
an internal bus hold (e.g. FSEL, TXEN, MODE) must be tied to a valid logic level during shutdown or standby Mode.
Table 5. Mode Transition Use Cases
MODE TRANSITION USE CASE TRANSITION SPECIFICS
Shutdown -> Standby Set TXEN high to enable 1. TXEN high > 10 μs
transmitter
2. Transmitter enters Standby mode
a. All outputs are in high-impedance state.
b. Transmitter turns on clock input monitor
Standby-> Acquire DCLK input activity detected 1. DCLK input monitor detects clock input activity;
2. Outputs remain in high-impedance state.
3. PLL circuit is enabled
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