Datasheet

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FEATURES

APPLICATIONS

DESCRIPTION

Scale = 50 ps/div

Scale = 75 mV/div

IN OUT

GND

SN65LVDS20

SN65LVP20

SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005

LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE

• 2.5-V or 3.3-V Supply Operation

• Low-Voltage PECL Input and Low-Voltage • 2-mm x 2-mm Small-Outline

PECL or LVDS Outputs No-Lead Package

• Signaling Rates to 4 Gbps or Clock Rates

to 2 GHz

• PECL-to-LVDS Translation

– 120-ps Output Transition Times

• Data or Clock Signal Amplification

– Less than 45 ps Total Jitter

– Less than 630 ps Propagation Delay Times

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater.

The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and

repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low

radiated emissions and minimal added jitter.

The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the

SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A

high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential

transmission lines with nominally 100- Ω characteristic impedance.

Both devices provide a voltage reference (V

) of typically 1.35 V below V

for use in receiving single-ended

PECL input signals. When not used, V

should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

FUNCTION DIAGRAM

Figure 1. SN65LVDS20 Output Eye Pattern With

4-Gbps PRBS Input

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE FEATURES • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Signaling Rates to 4 Gbps or Clock Rates to 2 GHz – 120-ps Output Transition Times – Less than 45 ps Total Jitter – Less than 630 ps Propagation Delay Times • • 2.5-V or 3.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) TYP (1) MAX RL = 100 Ω, EN at 0 V, Other inputs open 35 45 Outputs unloaded, EN at 0 V, Other inputs open 19 24 116 160 63 86 VCC - 1.35 VCC - 1.
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SN65LVDS20 SN65LVP20 www.ti.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) INPUT dVOC(SS) VOC(PP) VOC Figure 3. VOC Definitions VCC 1.2 V 1.125 V VIA 1.5 V VIB t PHL t PLH VOY − VOZ 80% 100% 50% tf tr 20% Figure 4. Propagation Delay and Transition Time Test Waveforms 50 Cable, X Y cm, SMA Coax Connectors, 4 Places HP3104 Pattern Generator Note A TDS Oscilloscope with TJIT3 Analysis Pack Device Under Test 50 50 DC Figure 5.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) VCC 1.2 V VIA 1.5 V VIB VI to EN 2V 1.4 V t PZH t PZL 0.8 V t PHZ t PLZ 0V VOY − VOZ 80% 50% 20% Figure 6.
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SN65LVDS20 SN65LVP20 www.ti.
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SN65LVDS20 SN65LVP20 www.ti.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) LVP20 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PERIOD JITTER vs FREQUENCY 5 476 4 tPHL Period Jitter − ps Propagation Delay Time − ps 500 452 tPLH 428 3 LVDS20 2 LVP20 1 404 380 −40 0 −20 0 20 40 60 80 0 100 400 1200 1600 Figure 13. Figure 14.
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SN65LVDS20 SN65LVP20 www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) PHASE NOISE OF SN65LVP20 PHASE NOISE OF SN65LVP20 −40 −40 −50 −60 −50 Blue = Device Green = Source −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 −140 −150 −150 −160 100 1k 10 k 100 k 1M 10 M 100 M Figure 19. Frequency Offset From 155.
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SN65LVDS20 SN65LVP20 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN65LVDS20DRFR WSON DRF 8 SN65LVDS20DRFT WSON DRF SN65LVP20DRFR WSON DRF SN65LVP20DRFT WSON DRF SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 8.8 2.3 2.3 1.0 4.0 8.0 Q2 8 250 330.0 8.8 2.3 2.3 1.0 4.0 8.0 Q2 8 3000 330.0 8.8 2.3 2.3 1.0 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS20DRFR WSON DRF 8 3000 337.0 343.0 29.0 SN65LVDS20DRFT WSON DRF 8 250 337.0 343.0 29.0 SN65LVP20DRFR WSON DRF 8 3000 337.0 343.0 29.0 SN65LVP20DRFT WSON DRF 8 250 337.0 343.0 29.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.