Datasheet

V
ID
V
O
10 pF,
2 Places
15 pF
100 Ω
†
1000 Ω
1000 Ω
100 Ω
V
IC
V
ID
V
O
V
ID
V
O
V
IT+
0 V
−100 mV
100 mV
0 V
V
IT−
†
Remove for testing LVDT device.
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns.
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
+
−
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. V
IT+
and V
IT-
Input Voltage Threshold Test Circuit and Definitions
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2