Datasheet

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V
OC
Z
Y
Input
C
L
= 10 pF
(2 Places)
3 V
0 V
V
OC(PP)
V
OC(SS)
V
OC
49.9 Ω, ±1% (2 Places)
Driver Enable
1.2 V
Z
Y
0.8 V or 2 V
49.9 Ω, ±1% (2 Places)
C
L
= 10 pF
(2 Places)
DE
V
OY
V
OZ
2 V
0.8 V
t
dis
t
en
t
dis
t
en
1.4 V
~1.4 V
1.2 V
1.25 V
1.2 V
~1 V
1.15 V
DE
V
OY
or V
OZ
V
OZ
or V
OY
D at 2 V and input to DE
D at 0.8 V and input to DE
SN65LVDS179-EP , , SN65LVDS180-EP
SN65LVDS050-EP , SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
9
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