Datasheet

1A
1B
1Y
1Z
1DE
2A
2B
2Y
2Z
2DE
3A
3B
3Y
3Z
3DE
4A
4B
4Y
4Z
4DE
4X4
MUX
8
S10 - S41
Integrated 110-W Termination on LVDT Only
SN65LVDT125A
SN65LVDS125A
SLLS595C –OCTOBER 2003– REVISED JUNE 2011 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
SN65LVDS125A Pin Description
Pin Numbers Pin Description
S10 - S41 Inputs; Input channel to out output channel selection control pins
1A, 2A, 3A, 4A Inputs; Positive leg of LVDS data input
1B, 2B, 3B, 4B Inputs; Negative leg of LVDS data input
1Y, 2Y, 3Y, 4Y Outputs; Positive leg of LVDS data output
1Z, 2Z, 3Z, 4Z Outputs; Negative leg of LVDS data output
1DE, 2DE, 3DE, 4DE Inputs; Output port disable
V
CC
Input Voltage
GND Ground
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