Datasheet

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PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
S0
1DE
S1
2A
2B
GND
V
CC
V
CC
1Y
1Z
2DE
2Z
2Y
GND
D OR PW PACKAGE
(TOP VIEW)
1Y / 1Z1A / 1B
2A / 2B
2Y / 2Z
2DE
1DE
1Y / 1Z1A / 1B
2A / 2B
2Y / 2Z
2DE
1DE
1Y / 1Z
1A / 1B
2A / 2B 2Y / 2Z
2DE
1DE
1Y / 1Z1A / 1B
2A / 2B
2Y / 2Z
2DE
1DE
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
Circuit Function Table
INPUTS
(1)
OUTPUTS
(1)
LOGIC DIAGRAM
1V
ID
2V
ID
S1 S0 1DE 2DE 1V
OD
2V
OD
X X X X L L Z Z
> 100 mV X L L H L H Z
< -100 mV X L L H L L Z
< -100 mV X L L H H L L
> 100 mV X L L H H H H
> 100 mV X L L L H Z H
< -100 mV X L L L H Z L
> 100 mV X H L H L H Z
< -100 mV X H L H L L Z
< -100 mV < -100 mV H L H H L L
< -100 mV > 100 mV H L H H L H
> 100 mV < -100 mV H L H H H L
> 100 mV > 100 mV H L H H H H
X > 100 mV H L L H Z H
X < -100 mV H L L H Z L
X > 100 mV L H H L H Z
X < -100 mV L H H L L Z
X < -100 mV L H H H L L
X > 100 mV L H H H H H
X > 100 mV L H L H Z H
X < -100 mV L H L H Z L
X > 100 mV H H H L H Z
X < -100 mV H H H L L Z
< -100 mV < -100 mV H H H H L L
< -100 mV > 100 mV H H H H H L
> 100 mV < -100 mV H H H H L H
> 100 mV > 100 mV H H H H H H
> 100 mV X H H L H Z H
< -100 mV X H H L H Z L
(1) H = high level, L = low level, Z = high impedance, X = don't care
5