Datasheet

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TIMING CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
SET
Input to select setup time 0 ns
t
HOLD
Input to select hold time 0.5 ns
t
SWITCH
Select to switch output 1 2 2.6 ns
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 400 650 900 ps
t
PHL
Propagation delay time, high-to-low-level output 400 650 900 ps
See Figure 4
t
r
Differential output signal rise time (20% - 80%) 280 ps
t
f
Differential output signal fall time (20% - 80%) 280 ps
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|)
(2)
10 50 ps
t
sk(pp)
Part-to-part skew
(3)
V
ID
= 0.2 V 100 ps
t
jit(per)
Period jitter, rms (1 standard deviation)
(4)
750 MHz clock input
(5)
1 2.2 ps
t
jit(cc)
Cycle-to-cycle jitter (peak)
(4)
750 MHz clock input
(6)
10 17 ps
t
jit(pp)
Peak-to-peak jitter
(4)
1.5 Gbps 2
23
–1 PRBS input
(7)
33 65 ps
t
jit(det)
Deterministic jitter, peak-to-peak
(4)
1.5 Gbps 2
7
–1 PRBS input
(8)
17 50 ps
t
PHZ
Propagation delay time, high-level-to-high-impedance output See Figure 5 6 8 ns
t
PLZ
Propagation delay time, low-level-to-high-impedance output See Figure 5 6 8 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output See Figure 5 4 6 ns
t
PZL
Propagation delay time, high-impedance-to-low-level output See Figure 5 4 6 ns
t
sk(o)
Output skew
(9)
15 40 ps
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Jitter is specified by design and characterization. Stimulus jitter has been subtracted.
(5) Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps (20% to 80%), measured over 1000 samples.
(6) Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps (20% to 80%).
(7) Input voltage = V
ID
= 200 mV, 2
23
–1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%), measured over 200 k samples.
(8) Input voltage = V
ID
= 200 mV, 2
7
–1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%).
(9) Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together.
4