SN65LVDS122EVM User’s Guide March 2003 High-Performance Linear/Interface Products SLLU056A
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 3 V to 3.6 V specified in this User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . .
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Chapter 1 This chapter gives a brief overview of the SN65LVDS122EVM and highlights the high-speed performance and functionality of the SN65LVDS122, 2x2 cross-point switch. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview 1.1 Overview The SN65LVDS122 is a 1.5-Gbps 2x2 cross-point switch. The four different functions that the SN65LVDS122 provides are shown in Figure 1–1. The function of the SN65LVDS122 is selected via pins S0 and S1. Control pins 1DE and 2DE enable or disable the outputs. The output levels of this device are LVDS, while the receiver has a wide input common-mode voltage range with an ability to accept LVPECL and CML signaling levels in addition to LVDS. Figure 1–1.
Signal Paths 1.2 Signal Paths The signal paths on this EVM include eight edge-launch SMA connectors (J1–J8) for high-speed data transmission, two jumpers (W1, W2) for active switch logic control, two jumpers (W3, W4) for static switch logic control, one jumper (J9) for enabling and disabling the outputs, and three banana jacks (J10, J11, J12) for power and ground connections.
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Chapter 2 This chapter describes the equipment, setup, and operation of the SN65LVDS122EVM. Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.
Overview 2.1 Overview TIA/EIA–644 specifies the LVDS driver output characteristics such that it maintains at least 247 mV across a 100-Ω differential load. This requirement includes the effects of up to 32 standard receivers with their ground reference up to 1 V different from that of the driver. This common-mode loading limitation of LVDS drivers affects how they are observed and much of the test set up that follows.
Applying an Input 2.2 Applying an Input When using a general-purpose signal generator with 50-Ω output impedance, make sure that the signal levels are between 0 V and 4 V with respect to J12, device under test ground (DUT GND), designated as VEE. Inputs should be applied to the SMA connectors J1, J2, J5, and J6. Matched cable lengths must be used when connecting the signal generator to the EVM to avoid inducing skew between the noninverting and inverting inputs.
Observing an Output 2.3 Observing an Output When the SN65LVDS122 EVM is connected directly to an oscilloscope with 50–Ω internal terminations to ground; resistors R4, R5, R6, and R7 are not needed (the EVM is shipped without R4–R7 installed). All external cabling needs to be matched in length to prevent skew between inverting and noninverting signals and between channels. The three power jacks (J10, J11, and J12) are used to provide power and a ground reference for the EVM.
Typical Test Results 2.4 Typical Test Results Figure 2–4 is a typical result obtained with the EVM setup shown in Figure 2–1. The upper waveform is the difference voltage between channels 1 and 2 of the oscilloscope and the lower trace is the difference voltage between channels 3 and 4. The DUT was configured to send the 1B/1A inputs to the outputs 2Z/2Y and inputs 2A/2B to outputs 1Y/1Z by setting 1DE and 2DE to a high level and by setting W3 and W4 to VCC. The stimuli were a 223–1 PRBS to J1 and J2 at 1.
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Chapter 3 This chapter provides the SN65LVDS122EVM schematic, board layers, and bill of materials. Topic Page 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Board Layout Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 3.1 Schematic Figure 3–1.
Board Layout Patterns 3.2 Board Layout Patterns Figure 3–2. SN65LVDS122EVM Silk Screen Figure 3–3. Signal Layer and GND Fill Figure 3–4.
Board Layout Patterns Figure 3–5. Layer 3 Split VCC amd VEE Figure 3–6. Layer 4 GND Plane Figure 3–7. PCB Fabrication Notes and Stackup Notes: 1) PWB to be fabricated to meet or exceed IPC-6012, Class 3 standards and workmanship conform to IPC-A-600, Class 3 current revisions 2) Board material and construction to be UL approved and marked on the finished board. 3) Laminate materal: Copper-clad NELCO N4000-13 (DO NOT USE—13SI) 4) Copper weight: 1 oz finished 5) Finished thickness: 0.62” ±0.
Bill of Materials 3.3 Bill of Materials Table 3–1. Bill of Materials for SN65LVDS122EVM—Rev A.PCB Comment Pattern Qty. Components 0.001 µF, 25 V, 5% 603 1 C9 0.01 µF, 50 V, ±10% 603 1 C2, C5 0.1 µF, 50 V, 5% 1206 2 C3, C4 100 Ω, 1/4 Watt, 1% 402 2 R8, R10 10 µF, 35 V, 10% 7343 2 C7, C8 1 µF, 25 V +80 –20% 1206 1 C6, C1 2-position jumper 2pos_jump 2 W1, W2 3-position jumper 3pos_jump 2 W3, W4 3×2×0.1 2×3×0.1 1 J9 49.
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