Datasheet
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS116
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
ITH+
Positive-going differential input voltage threshold 100
See Figure 1 and Table 1 mV
V
ITH–
Negative-going differential input voltage threshold –100
|V
OD
| Differential output voltage magnitude 247 340 454
R
L
= 100 Ω , V
ID
= ± 100 mV,
mV
Change in differential output voltage magnitude be-
See Figure 1 and Figure 2
∆ |V
OD
| –50 50
tween logic states
V
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output volt-
∆ V
OC(SS)
See Figure 3 50 50
age between logic states
mV
V
OC(PP)
Peak-to-peak common-mode output voltage 50 150
Enabled, R
L
= 100 Ω 84 115
I
CC
Supply current mA
Disabled, ENx = V
CC
or ENx = 0 V 3.2 6
V
I
= 0 V –2 –20
I
I
Input current (A or B inputs)
(2)
µA
V
I
= 2.4 V –1.2
I
I(OFF)
Power-off input current (A or B inputs) V
CC
= 1.5 V, V
I
= 2.4 V 20 µA
ENx, S0, S1 20
I
IH
High-level input current V
IH
= 2 V µA
ENx, SM –20
ENx, S0, S1 10
I
IL
Low-level input current V
IL
= 0.8 V µA
ENx, SM –10
V
OY
or V
OZ
= 0 V ± 24
I
OS
Short-circuit output current mA
V
OD
= 0 V ± 12
I
OZ
High-impedance output current V
O
= 0 V or V
CC
± 1 µA
I
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 3.6 V ± 1 µA
C
IN
Input capacitance (A or B inputs) V
I
= 0.4 sin (4E6 π t) + 0.5 V 5
pF
C
O
Output capacitance (Y or Z outputs) V
I
= 0.4 sin (4E6 π t) + 0.5 V 9.4
(1) All typical values are at 25 ° C and with a 3.3-V supply.
(2) The non-algebraic convention, where the more positive (least negative) limit is designated minimum, is used in this data sheet for the
input current (I
I
) only.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.2 3.1 4.7 ns
t
PHL
Propagation delay time, high-to-low-level output 2.2 3.1 4.7 ns
t
r
Differential output signal rise time 0.3 0.8 1.2 ns
R
L
= 100 Ω , C
L
= 10 pF,
t
f
Differential output signal fall time 0.3 0.8 1.2 ns
See Figure 4
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|)
(2)
140 500 ps
t
sk(o)
Output skew, channel-to-channel
(3)
100 300 ps
t
sk(pp)
Part-to-part skew
(4)
1.5 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output 5.7 15 ns
t
PZL
Propagation delay time, high-impedance-to-low-level output 7.7 15 ns
See Figure 5
t
PHZ
Propagation delay time, high-level-to-high-impedance output 3.2 15 ns
t
PLZ
Propagation delay time, low-level-to-high-impedance output 3.2 15 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.
(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(3) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
measured at any two outputs.
(4) t
sk(pp)
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5