Datasheet

www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
A4Z
A4Y
A3Z
A3Y
A2Z
A2Y
A1Z
A1Y
S0
A
B
B2Z
B2Y
B1Z
B1Y
B4Z
B4Y
B3Z
B3Y
C2Z
C2Y
C1Z
C1Y
C4Z
C3Z
C4Y
C3Y
D2Z
D2Y
D1Z
D1Y
D4Z
D4Y
D3Z
D3Y
SM
S1
ENA
ENA
ENB
ENB
ENC
ENC
END
END
SN65LVDS116
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
2