Datasheet

www.ti.com
APPLICATION INFORMATION
FAIL SAFE
Rt = 100 (Typ)
300 k 300 k
V
CC
V
IT
2.3 V
A
B
Y
INPUT LEVEL TRANSLATION
V
DD
50
25
50
A
B
1/2 V
DD
0.1 µF
LVDS Receiver
SN65LVDS116
SLLS370D SEPTEMBER 1999 REVISED FEBRUARY 2005
A common problem with differential signaling applications is how the system responds when no differential
voltage is present on the signal pair. The SN65LVDS116 receiver is like most differential line receivers, in that its
output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and
within its recommended input common-mode voltage range. Hovever, TI LVDS receivers handle the open-input
circuit situation differently.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near V
CC
through 300-k resistors as shown in Figure 12 . The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
Figure 12. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in Figure 12 . Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
An LVDS receiver can be used to receive various other types of logic signals. Figure 13 through Figure 21 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Figure 13. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
11