Datasheet

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Y
Z
Input
50 pF
49.9 Ω ± 1% (2 Places)
V
OC
V
O
V
OC(PP)
V
OC(SS)
1 V
1.4 V
V
I
Input
V
I
Y
Z
V
OD
Input
C
L
= 10 pF
(2 Places)
100 Ω ± 1 %
1.4 V
1.2 V
1 V
t
PLH
t
PHL
100%
80%
20%
0%
Input
Output
0 V
t
f
t
r
V
OD(H)
V
OD(L)
V
IB
V
IA
A
B
SN65LVDS109
SN65LVDS117
SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
8