Datasheet

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LOGIC DIAGRAM (POSITIVE LOGIC)
B2Z
B2Y
B1Z
B1Y
A2Z
A2Y
A1Z
A1Y
ENA
ENM
ENB
1A
1B
C2Z
C2Y
C1Z
C1Y
ENC
D2Z
D2Y
D1Z
D1Y
END
E2Z
E2Y
E1Z
E1Y
ENE
F2Z
F1Z
ENF
F2Y
F1Y
2A
2B
G2Z
G2Y
G1Z
G1Y
ENG
H2Z
H2Y
H1Z
H1Y
ENH
B2Z
B2Y
B1Z
B1Y
A2Z
A2Y
A1Z
A1Y
ENA
ENM
ENB
1A
1B
C2Z
C2Y
C1Z
C1Y
ENC
D2Z
D2Y
D1Z
D1Y
END
SN65LVDS109 SN65LVDS117
2A
2B
SN65LVDS109
SN65LVDS117
SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
2