Datasheet

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C
D
C
D
C
D
Output Pair Disabled
DUAL n–PORT REPEATER
C
D
DESTINATION
EQUIPMENT/
BOARD #1
DESTINATION
EQUIPMENT/
BOARD #2
DESTINATION
EQUIPMENT/
BOARD #n
SOURCE
EQUIPMENT/
BOARD
INPUT LEVEL TRANSLATION
V
DD
50
25
50
A
B
1/2 V
DD
0.1 µF
LVDS Receiver
SN65LVDS109
SN65LVDS117
SLLS369F AUGUST 1999 REVISED FEBRUARY 2005
APPLICATION INFORMATION (continued)
The enable inputs provided for each output pair may be used to turn on or off any of the paths. This function is
required to prevent radiation of signals from the unterminated signal lines on open connectors, such as when
boards or devices are being swapped in the end equipment. The individual bank enables are also required if
redundant paths are being utilized for reliability reasons.
The diagram below shows how a pair of clock (C) and data (D) input signals is being identically repeated out two
of the available output pairs. A third output pair is shown in the disabled state.
Figure 16. LVDS Repeating Splitter Application Example Showing Individual Path Control
An LVDS receiver can be used to receive various other types of logic signals. Figure 17 through Figure 25 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Figure 17. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
15