Datasheet
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0
100
200
300
400
500
600
700
800
900
0 200 400 600 800
Signaling Rate − Mbps
V
CC
= 3.6 V
V
CC
= 3 V
Peak-to-Peak Jitter − ps
T
A
= 25C
0
2
4
6
8
10
12
14
16
18
20
0 100 200 300 400 500
Clock Frequency − MHz
Peak-to-Peak Jitter − ps
T
A
= 25C
V
CC
= 3.6 V
V
CC
= 3 V
SN65LVDS109
SN65LVDS117
SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS (continued)
SN65LVDS109
P-P EYE-PATTERN JITTER
vs
PRBS SIGNALING RATE
NOTES: Input: 2
15
PRBS with peak-to-peak jitter < 100 ps at 100 Mbps, all outputs enabled and loaded with differential
100- Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF ceramic 0603-style capacitors placed 1
cm from the device.
Figure 10.
SN65LVDS109
P-P PERIOD JITTER
vs
CLOCK FREQUENCY
NOTES: Input: 50% duty cycle square wave with jitter period < 10 ps at 100 MHz, all outputs enabled and loaded with
differential 100- Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF ceramic 0603-style capacitors
1 cm from the device.
Figure 11.
11