Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers LVDS 400 Mbit/s TSSOP 38

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FEATURES

DESCRIPTION

GND

ENM

ENA

ENB

ENC

END

GND

ENE

ENF

ENG

ENH

GND

A1Y

A1Z

A2Y

A2Z

B1Y

B1Z

B2Y

B2Z

C1Y

C1Z

C2Y

C2Z

D1Y

D1Z

D2Y

D2Z

E1Y

E1Z

E2Y

E2Z

F1Y

F1Z

F2Y

F2Z

G1Y

G1Z

G2Y

G2Z

H1Y

H1Z

H2Y

H2Z

SN65LVDS117

DGG PACKAGE

(TOP VIEW)

GND

ENM

ENA

ENB

GND

ENC

END

GND

A1Y

A1Z

A2Y

A2Z

B1Y

B1Z

B2Y

B2Z

C1Y

C1Z

C2Y

C2Z

D1Y

D1Z

D2Y

D2Z

SN65LVDS109

DBT PACKAGE

(TOP VIEW)

SN65LVDS109

SN65LVDS117

SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

The intended application of these devices, and the

LVDS signaling technique, is for point-to-point or

• Two Line Receivers and Eight ('109) or

point-to-multipoint (distributed simplex) baseband

Sixteen ('117) Line Drivers Meet or Exceed the

data transmission on controlled impedance media of

Requirements of ANSI EIA/TIA-644 Standard

approximately 100 Ω . The transmission media may

• Typical Data Signaling Rates to 400 Mbps or

be printed-circuit board traces, backplanes, or cables.

Clock Frequencies to 400 MHz

The large number of drivers integrated into the same

silicon substrate, along with the low pulse skew of

• Outputs Arranged in Pairs From Each Bank

balanced signaling, provides extremely precise timing

• Enabling Logic Allows Individual Control of

alignment of the signals being repeated from the

Each Driver Output Pair, Plus All Outputs

inputs. This is particularly advantageous for im-

• Low-Voltage Differential Signaling With plementing system clock and data distribution trees.

Typical Output Voltage of 350 mV and a 100- Ω

The SN65LVDS109 and SN65LVDS117 are

Load

characterized for operation from –40 ° C to 85 ° C.

• Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,

SSTL, or HSTL Outputs With External

Termination Networks

• Propagation Delay Times < 4.5 ns

• Output Skew Less Than 550 ps Bank Skew

Less Than150 ps Part-to-Part Skew Less Than

1.5 ns

• Total Power Dissipation Typically <500 mW

With All Ports Enabled and at 200 MHz

• Driver Outputs or Receiver Input Equals High

Impedance When Disabled or With V

< 1.5 V

• Bus-Pin ESD Protection Exceeds 12 kV

• Packaged in Thin Shrink Small-Outline

Package With 20-Mil Terminal Pitch

The SN65LVDS109 and SN65LVDS117 are con-

figured as two identical banks, each bank having one

differential line receiver connected to either four

('109) or eight ('117) differential line drivers. The

outputs are arranged in pairs having one output from

each of the two banks. Individual output enables are

provided for each pair of outputs and an additional

enable is provided for all outputs.

The line receivers and line drivers implement the

electrical characteristics of low-voltage differential

signaling (LVDS). LVDS, as specified in EIA/TIA-644,

is a data signaling technique that offers low power,

low noise emission, high noise immunity, and high

switching speeds. (Note: The ultimate rate and dis-

tance of data transfer is dependent upon the attenu-

ation characteristics of the media, the noise coupling

to the environment, and other system characteristics.)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN65LVDS109 SN65LVDS117 www.ti.
PAGE 2
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 SELECTION GUIDE TO LVDS SPLITTERS The SN65LVDS109 and SN75LVDS117 are both members of a family of LVDS splitters and repeaters. A brief overview of the family is provided by Table 1. Table 1.
PAGE 4
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) –0.5 V to 4 V Enable inputs Input voltage range –0.5 V to 6 V A, B, Y or Z Electrostatic discharge –0.
PAGE 5
SN65LVDS109 SN65LVDS117 www.ti.
PAGE 6
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.6 2.8 4.5 tPHL Propagation delay time, high-to-low-level output 1.6 2.8 4.5 tr Differential output signal rise time 0.3 0.8 1.2 tf Differential output signal fall time 0.3 0.8 1.
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SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION IOY IIA IIB VID A Y B Z IOZ VOD VOY VOC VIA VOZ VIB (VOY + VOZ)/2 Figure 1. Voltage and Current Definitions Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.
PAGE 8
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 49.9 Ω ± 1% (2 Places) Y Input Input VI 1.4 V VI 1V Z 50 pF VOC(PP) VOC(SS) VOC VO A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
PAGE 9
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 Y 1 V or 1.4 V 49.9 Ω ± 1% (2 Places) Z 1.4 V or 1 V + Inputs EN CL = 10 pF (2 Places) VOY tPZH tPHZ VOY or VOZ 100%, ≅ 1.4 V 50% 0%, 1.2 V tPZL A. 1.2 V – 2V 1.4 V 0.8 V Input VOZ or VOY VOZ tPLZ 100%, 1.2 V 50% 0%, ≅ 1 V All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns .
PAGE 10
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS SN65LVDS117 SUPPLY CURRENT vs SWITCHING FREQUENCY 140 220 120 200 VCC = 3.6 V I CC − Supply Current − mA I CC − Supply Current − mA SN65LVDS109 SUPPLY CURRENT vs SWITCHING FREQUENCY 100 VCC = 3 V 80 60 VCC = 3.3 V 40 180 VCC = 3.6 V 160 VCC = 3 V 140 120 VCC = 3.
PAGE 11
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) SN65LVDS109 P-P EYE-PATTERN JITTER vs PRBS SIGNALING RATE 900 TA = 25 C 800 VCC = 3.6 V Peak-to-Peak Jitter − ps 700 600 500 VCC = 3 V 400 300 200 100 0 0 200 400 600 800 Signaling Rate − Mbps NOTES: Input: 215 PRBS with peak-to-peak jitter < 100 ps at 100 Mbps, all outputs enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.
PAGE 12
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) SN65LVDS117 P-P EYE-PATTERN JITTER vs PRBS SIGNALING RATE 900 TA = 25 C 800 Peak-to-Peak Jitter − ps 700 VCC = 3.6 V 600 500 VCC = 3 V 400 300 200 100 0 0 100 200 300 400 Signaling Rate − Mbps NOTES: Input: 215 PRBS with peak-to-peak jitter < 115 ps at 100 Mbps, all outputs enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.
PAGE 13
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) Figure 14.
PAGE 14
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION FAIL SAFE A common problem with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range.
PAGE 15
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) The enable inputs provided for each output pair may be used to turn on or off any of the paths. This function is required to prevent radiation of signals from the unterminated signal lines on open connectors, such as when boards or devices are being swapped in the end equipment. The individual bank enables are also required if redundant paths are being utilized for reliability reasons.
PAGE 16
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) VDD 50 Ω A 50 Ω B 1.35 V < VTT < 1.65 V 0.1 µF LVDS Receiver Figure 18. Center-Tap Termination (CTT) 1.14 V < VTT < 1.26 V VDD 50 Ω 1 kΩ 50 Ω A B 0.1 µF 2 kΩ LVDS Receiver Figure 19. Gunning Transceiver Logic (GTL) Z0 Z0 A B 1.47 V < VTT < 1.62 V 0.1 µF Figure 20.
PAGE 17
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) 3.3 V 3.3 V 50 Ω 120 Ω 120 Ω 33 Ω ECL A 50 Ω 33 Ω B 51 Ω 51 Ω LVDS Receiver Figure 21. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 5V 5V 50 Ω 82 Ω 82 Ω 100 Ω ECL A 50 Ω 100 Ω 33 Ω B 33 Ω LVDS Receiver Figure 22.
PAGE 18
SN65LVDS109 SN65LVDS117 www.ti.com SLLS369F – AUGUST 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) 3.3 V 3.3 V 7.5 kΩ A B 7.5 kΩ 0.1 µF LVDS Receiver Figure 23. 3.3-V CMOS 5V 5V 10 kΩ 560 Ω A B 560 Ω 3.32 kΩ 0.1 µF LVDS Receiver Figure 24. 5-V CMOS 5V 5V 10 kΩ 470 Ω A B 3.3 V 4.02 kΩ Figure 25. TTL 18 0.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS117DGGR Package Package Pins Type Drawing TSSOP DGG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.3 1.7 12.0 24.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS117DGGR TSSOP DGG 64 2000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.