Datasheet

www.ti.com
APPLICATION INFORMATION
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ 300 kΩ
V
CC
V
IT
≈ 2.3 V
A
B
Y
CLOCK DISTRIBUTION
SN65LVDS108
SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005
A common problem with differential signaling applications is how the system responds when no differential
voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output
logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within
its recommended input common-mode voltage range. Hovever, TI LVDS receivers handles the open-input circuit
situation differently.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near V
CC
through 300-k Ω resistors as shown in Figure 12 . The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
Figure 12. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in Figure 12 . Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
The SN65LVDS108 device solves several problems common to the distribution of timing critical clock and data
signals. These problems include:
• Excessive skew between the signal paths
• Noise pickup over long signaling paths
• High power consumption
• Control of which signal paths are enabled or disabled
• Elimination of radiation from unterminated lines
Buffering and splitting the signal on the same silicon die minimizes corruption of the timing relation between the
copies of the signal. Buffering and splitting the signal in separate devices will introduce considerably higher levels
of uncontrolled timing skew between the signals. Higher speed operation and more timing tolerance for other
components of the system is enabled by the tighter system timing budgets provided by the single die
implementations of the SN65LVDS108.
The use of LVDS signaling technology for both the inputs and the outputs provides superior common-mode and
noise tolerance compared to single-ended I/O technologies. This is particularly important because the signals
that are being distributed must be transmitted over longer distances, and at higher rates, than can be
accommodated with single-ended I/Os. In addition, LVDS consumes considerably less power than other
high-performance differential signaling schemes.
10