Datasheet

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Y
Z
49.9 Ω ± 1% (2 Places)
V
OC
V
O
V
OC(PP)
V
OC(SS)
0 VA
3 V
C
L
= 10 pF
(2 Places)
(see Note B)
Input
(see Note A)
Y
Z
V
OD
Input
(see Note A)
C
L
= 10 pF
(2 Places)
(see Note B)
100 Ω ± 1%
3 V
1.5 V
0 V
t
PLH
t
PHL
100%
80%
20%
0%
Input
Output
0 V
t
f
t
r
V
OD(H)
V
OD(L)
V
IA
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns.
B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
OC(PP)
is made
on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 8. 'LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns.
B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 9. 'LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
9