Datasheet

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SN65LVDS104 ELECTRICAL CHARACTERISTICS
SN65LVDS104 SWITCHING CHARACTERISTICS
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold 100
See Figure 1 and Table 1 mV
V
IT-
Negative-going differential input voltage threshold –100
|V
OD
| Differential output voltage magnitude 247 340 454
R
L
= 100 Ω , V
ID
= ± 100 mV,
mV
Change in differential output voltage magnitude between logic
See Figure 1 and Figure 2
∆ |V
OD
| –50 50
states
V
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltage be-
∆ V
OC(SS)
See Figure 3 –50 50 mV
tween logic states
V
OC(PP)
Peak-to-peak common-mode output voltage 25 150 mV
Enabled, R
L
= 100 Ω 23 35 mA
I
CC
Supply current
Disabled 3 8 mA
V
I
= 0 V –2 –11 –20
I
I
Input current (A or B inputs) µA
V
I
= 2.4 V –1.2 –3
I
I(OFF)
Power-off Input current V
CC
= 1.5 V, V
I
= 2.4 V 20 µA
I
IH
High-level input current (enables) V
IH
= 2 V 20 µA
I
IL
Low-level input current (enables) V
IL
= 0.8 V 10 µA
V
OY
or V
OZ
= 0 V ± 10 mA
I
OS
Short-circuit output current
V
OD
= 0 V ± 10 mA
I
OZ
High-impedance output current V
O
= 0 V or 2.4 V ± 1 µA
I
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 2.4 V ± 1 µA
C
IN
Input capacitance (A or B inputs) V
I
= 0.4 sin (4E6 π t) + 0.5 V 3 pF
V
I
= 0.4 sin (4E6 π t) + 0.5 V,
C
O
Output capacitance (Y or Z outputs) 9.4 pF
Disabled
(1) All typical values are at 25 ° C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.4 3.2 4.2 ns
t
PHL
Propagation delay time, high-to-low-level output 2.2 3.1 4.2 ns
t
r
Differential output signal rise time 0.3 0.8 1.2 ns
R
L
= 100 Ω , C
L
= 10 pF,
See Figure 4
t
f
Differential output signal fall time 0.3 0.8 1.2 ns
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) 150 500 ps
t
sk(o)
Channel-to-channel output skew
(2)
20 100 ps
t
sk(pp)
Part-to-part skew
(3)
1.5 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output 7.2 15 ns
t
PZL
Propagation delay time, high-impedance-to-low-level output 8.4 15 ns
See Figure 5
t
PHZ
Propagation delay time, high-level-to-high-impedance output 3.6 15 ns
t
PLZ
Propagation delay time, low-level-to-high-impedance output 6 15 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.
(2) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all drivers of a single device with all of their inputs connected
together.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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