5 V
100 Ω
A
B
5 V
LVDS Receiver
100 Ω
33 Ω
ECL
50 Ω
50 Ω
33 Ω
82 Ω82 Ω
3.3 V
A
B
3.3 V
LVDS Receiver
7.5 kΩ
0.1 µF
7.5 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Figure 28. Positive Emitter-Coupled Logic (PECL)
Figure 29. 3.3-V CMOS
17
