Datasheet

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A
B
1.47 V < V
TT
< 1.62 V
0.1 µF
LVDS Receiver
Z
0
Z
0
3.3 V
33 Ω
A
B
3.3 V
LVDS Receiver
33 Ω
51 Ω
ECL
50 Ω
50 Ω
51 Ω
120 Ω120 Ω
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Figure 26. Backplane Transceiver Logic (BTL)
Figure 27. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
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