Datasheet

www.ti.com
APPLICATION INFORMATION
INPUT LEVEL TRANSLATION
V
DD
50 Ω
25 Ω
50
Ω
A
B
1/2 V
DD
0.1 µF
LVDS Receiver
V
DD
50 Ω
50 Ω
A
B
1.35 V < V
TT
< 1.65 V
0.1 µF
LVDS Receiver
V
DD
A
B
1.14 V < V
TT
< 1.26 V
LVDS Receiver
2 kΩ
50 Ω
0.1 µF
50 Ω1 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
An LVDS receiver can be used to receive various other types of logic signals. Figure 23 through Figure 32 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Figure 23. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
Figure 24. Center-Tap Termination (CTT)
Figure 25. Gunning Transceiver Logic (GTL)
15