Datasheet
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0
100
200
300
400
500
600
0 100 200 300 400 500 600
Signaling Rate − Mbps
V
CC
= 3.6 V
V
CC
= 3 V
Peak-to-Peak Jitter − ps
T
A
= 25C
0
2
4
6
8
10
12
14
0 100 200 300 400 500 600
Clock Frequency − MHz
Peak-to-Peak Jitter − ps
T
A
= 25C
V
CC
= 3 V
V
CC
= 3.6 V
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS105 P-P EYE-PATTERN JITTER
vs
PRBS SIGNALING RATE
NOTES: Input: 2
15
PRBS with peak-to-peak Jitter < 147 ps at 100 Mbps, Test board adds about 43 ps p-p jitter. All outputs
enabled and loaded with differential 100- Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF
ceramic 0603-style capacitors 1 cm from the device.
Figure 21.
SN65LVDS105 P-P PERIOD JITTER
vs
CLOCK FREQUENCY
NOTES: Input: 50% duty cycle square wave with period jitter < 10 ps at 100 MHz. Test board adds about 5 ps p-p jitter. All
outputs enabled and loaded with differential 100- Ω loads, worst-case output, supply decoupled with 0.1-µF and
0.001-µF ceramic 0603-style capacitors 1 cm from the device.
Figure 22.
14