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50 Ω
V
OY
V
OZ
50 Ω
V
OD
+
-
V
CC
- 2V
+
-
1.4 V
1 V
t
PLH
0.4 V
0 V
V
IA
V
IB
V
ID
80%
100%
0%
t
PHL
20%
t
f
t
r
V
OD
0 V
Y
Z
A
B
V
ID
1 pF
V
IB
V
IA
V
OD
100 Ω
-0.4 V
50 Ω
50 Ω
V
CC
- 2V
+
-
OR
V
OD
0 V
CLOCK INPUT
1/fo
IDEAL OUTPUT
0 V
1/fo
ACTUAL OUTPUT
0 V
t
c(n)
0 V
PRBS INPUT
0 V
ACTUAL OUTPUT
0 V
PRBS OUTPUT
Period Jitter Cycle to Cycle Jitter
t
jit(per)
= |t
c(n)
- 1/fo|
t
c(n)
t
c(n+1)
t
jit(cc)
= |t
c(n)
- t
c(n+1)
|
t
jit(pp)
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 0.25 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 5. Timing Test Circuit and Waveforms
Figure 6. Driver Jitter Measurement Waveforms
6