Datasheet

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PARAMETER MEASUREMENT INFORMATION
Y
Z
A
B
V
ID
V
OD
V
IB
V
IA
V
O(Z)
V
O(Y)
I
IB
I
IA
V
IA
+V
IB
V
IC
2
V
OC
I
O
V
BB
V
BB
+
-
V
OD
100 Ω
3.74 kΩ
3.74 kΩ
_
+
0 V ≤ V
(test)
≤ 2.4 V
Y
Z
V
OC
49.9 Ω ±1%
Y
1 pF
V
OC(PP)
V
OC(SS)
V
OC
1.4 V
B
A
1.0 V
49.9 Ω ±1%
Z
A
V
ID
B
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 1. Voltage and Current Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES OUTPUT
(1)
INPUT VOLTAGE MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V H
1.15 V 1.25 V –100 mV 1.2 V L
4.0 V 3.9 V 100 mV 3.95 V H
3.9 V 4. 0 V –100 mV 3.95 V L
0.1 V 0.0 V 100 mV 0.05 V H
0.0 V 0.1 V –100 mV 0.05 V L
1.7 V 0.7 V 1000 mV 1.2 V H
0.7 V 1.7 V –1000 mV 1.2 V L
4.0 V 3.0 V 1000 mV 3.5 V H
3.0 V 4.0 V –1000 mV 3.5 V L
1.0 V 0.0 V 1000 mV 0.5 V H
0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
Figure 2. SN65LVDx100 Differential Output Voltage (V
OD
) Test Circuit
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 0.25 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the SN65LVDx100 Driver Common-Mode Output Voltage
5