Datasheet

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SWITCHING CHARACTERISTICS
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1 )
|V
OD
| Differential output voltage magnitude 247 340 454
See Figure 2 mV
Change in differential output voltage magni-
∆|V
OD
| –50 50
tude between logic states
V
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output
∆V
OC(SS)
See Figure 3 –50 50 mV
voltage between logic states
V
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mV
I
OS
Short-circuit output current V
O(Y)
or V
O(Z)
= 0 V –24 24 mA
I
OS(D)
Differential short-circuit output current V
OD
= 0 V –12 12 mA
SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1 )
50 Ω to V
CC
– 2 V, See Figure 4 V
CC
–1.25 V
CC
–1.02 V
CC
–0.9 V
V
OH
High-level output voltage
V
CC
= 3.3 V, 50-Ω load to 2.3 V 2055 2280 2405 mV
50 Ω to V
CC
- 2 V, See Figure 4 V
CC
–1.83 V
CC
–1.61 V
CC
–1.53 V
V
OL
Low-level output voltage
V
CC
= 3.3 V, 50-Ω load to 2.3 V 1475 1690 1775 mV
|V
OD
| Differential output voltage magnitude 50-Ω load to V
CC
– 2 V, SeeFigure 4 475 575 750 mV
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
'LVDx100 300 470 800
Propagation delay time,
t
PLH
ps
low-to-high-level output
'LVDx101 400 630 900
'LVDx100 300 470 800
Propagation delay time,
t
PHL
ps
high-to-low-level output
'LVDx100 See Figure 5 400 630 900
t
r
Differential output signal rise time (20%–80%) 220 ps
t
f
Differential output signal fall time (20%–80%) 220 ps
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|)
(2)
5 50 ps
t
sk(pp)
Part-to-part skew
(3)
V
ID
= 0.2 V, See Figure 5 100 ps
t
jit(per)
RMS period jitter
(4)
1 3.7 ps
1 GHz 50% duty cycle square wave input,
V
ID
= 200 mV, V
IC
= 1.2 V, See Figure 6
t
jit(cc)
Peak cycle-to-cycle jitter
(5)
6 23 ps
2 GHz PRBS, 2
23
–1 run length, V
ID
= 200 mV,
t
jit(pp)
Peak-to-peak jitter 28 65 ps
V
IC
= 1.2 V, See Figure 6
2 GHz PRBS, 2
7
–1 run length, V
ID
= 200 mV,
t
jit(det)
Peak-to-peak deterministic jitter
(6)
17 48 ps
V
IC
= 1.2 V, See Figure 6
(1) All typical values are at 25°C and with a 3.3 V supply.
(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(3) t
sk(pp)
is the magnitude of the time difference in propagation delay time between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 1000,000 cycles.
(5) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
(6) Deterministic jitter is the sum of pattern-dependent jitter and pulse-width distortion.
4