Datasheet
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
POWER DISSIPATION RATINGS
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
OUTPUT TERMINATION RESISTOR V
BB
PART NUMBER
(1)
PART MARKING PACKAGE
LVDS No Yes SN65LVDS100D DL100 SOIC
LVDS No Yes SN65LVDS100DGK AZK MSOP
LVDS Yes No SN65LVDT100D DE100 SOIC
LVDS Yes No SN65LVDT100DGK AZL MSOP
LVPECL No Yes SN65LVDS101D DL101 SOIC
LVPECL No Yes SN65LVDS101DGK AZM MSOP
LVPECL Yes No SN65LVDT101D DE101 SOIC
LVPECL Yes No SN65LVDT101DGK BAF MSOP
(1) Add the suffix R for taped and reeled carrier (i.e. SN65LVDS100DR).
over operating free-air temperature range unless otherwise noted
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 V
I
BB
V
BB
Output current ±0.5 mA
V
I
Voltage range, (A, B, Y, Z) 0 V to 4.3 V
V
O
V
ID
Differential voltage, |V
A
– V
B
| ('LVDT100 and 'LVDT101 only) 1 V
A, B, Y, Z, and GND ±5 kV
Human Body Model
(3)
ESD All pins ±2 kV
Charged-Device Model
(4)
All pins ±1500 V
P
D
Continuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
T
A
≤ 25°C DERATING FACTOR
(1)
T
A
= 85°C
PACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
DGK 377 mW 3.8 mW/°C 151 mW
D 481 mW 4.8 mW/°C 192 mW
(1) This is the inverse of the junction-to-ambient thermal resistance with no air flow installed on the JESD51-3 low effective thermal
conductivity test board for leadless surface mount packages.
2