Datasheet

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FAILSAFE CONSIDERATIONS

1.6 kΩ

100 Ω

3.3 V

SN65LVDS100, SN65LVDT100

SN65LVDS101, SN65LVDT101

SLLS516C – AUGUST 2002 – REVISED JUNE 2004

APPLICATION INFORMATION (continued)

Failsafe, in regard to a line receiver, usually means that the output goes to a defined logical state with no input

signal. To keep added jitter to an absolute minimum, the SN65LVDS100 does not include this feature. It does

exhibit 25 mV of input voltage hysteresis to prevent oscillation and keep the output in the last state prior to

input-signal loss (assuming the differential noise in the system is less than the hysteresis).

Should failsafe be required, it may be added externally with a 1.6-kΩ pull-up resistor to the 3.3-V supply and a

1.6-kΩ pull-down resistor to ground as shown in Figure 45 The default output state is determined by which line is

pulled up or down and is the user's choice. The location of the 1.6-kΩ resistors is not critical. However the 100-Ω

resistor should be located at the end of the transmission line.

Figure 45. External Failsafe Circuit

Addition of this external failsafe will reduce the differential noise margin and add jitter to the output signal. The

roughly 100-mV steady-state voltage generated across the 100-Ω resistor adds (or subtracts) from the signal

generated by the upstream line driver. If the line driver's differential output is symmetrical about zero volts, then

the input at the receiver will appear asymmetrical with the external failsafe. Perhaps more important, is the extra

time it takes for the input signal to overcome the added failsafe offset voltage.

In Figure 46 and using an external failsafe, the high-level differential voltage at the input of the SN65LVDS100

reaches 340 mV and the low-level –400 mV indicating a 60-mV differential offset induced by the external failsafe

circuitry. The figure also reveals that the lowest peak-to-peak time jitter does not occur at zero-volt differential

(the nominal input threshold of the receiver) but at –60 mV, the failsafe offset.

The added jitter from external failsafe increases as the signal transition times are slowed by cable effects. When

a ten-meter CAT-5 UTP cable is introduced between the driver and receiver, the zero-crossing peak-to-peak jitter

at the receiver output adds 250 ps when the external failsafe is added with this specific test set up. If external

failsafe is used in conjunction with the SN65LVDS100, the noise margin and jitter effects should be budgeted.