Datasheet

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Device
Under
Test
C
L
R
L
S
1
V
CC
R
IN+
R
IN–
R
OUT
EN
EN
50 Ω
Generator
1/4 65LVDS048A
C
L
Includes Load and Test Jig Capacitance.
S
1
= V
CC
for t
PZL
and t
PLZ
Measurements.
S
1
= GND for t
PZH
and t
PHZ
Measurements.
t
PLZ
t
PZL
t
PHZ
t
PZH
0.5 V
0.5 V
50%
50%
3 V
0 V
3 V
0 V
V
CC
V
OL
V
OH
GND
EN When EN = GND or Open
EN
When EN = V
CC
Output When
V
ID
= –100 mV
Output When
V
ID
= 100 mV
1.5 V 1.5 V
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Receiver 3-State Delay Test Circuit
Figure 4. Receiver 3-State Delay Waveforms
6
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