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PARAMETER MEASUREMENT INFORMATION
A
Z
V
OD
V
I
(V
OY
+V
OZ
)/2
I
OY
I
OZ
V
OZ
V
OY
V
OC
Y
I
I
V
OD
_
+
R
L
3.75 kΩ
3.75 kΩ
Y
Z
Input
0 V ≤ V
test
≤ 2.4 V
V
OC
Y
Z
Input
49.9 Ω ± 1%(2 Places)
A
C
L
= 10 pF
(2 Places)
A
V
OC
V
OC(PP)
V
OC(SS)
3 V
0 V
V
OD
Y
Z
Input
C
L
= 10 pF
(2 Places)
t
PLH
t
PHL
3 V
1.5 V
0 V
100%
80%
20%
0%
t
f
t
r
0 V
Input
Output
V
OD(H)
V
OD(L)
100 Ω
SN65LVDM31
SLLS417C – MARCH 2000 – REVISED MAY 2001
Figure 1. Driver Voltage and Current Definitions
Figure 2. V
OD
Test Circuit
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the DUT. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the DUT.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
4
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