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2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
V
OD(H)
V
OD(L)
Output
Input
t
PHL
t
PLH
t
f
t
r
_
+
V
OD
50 Ω
3.75 kΩ
3.75 kΩ
0 ≤ V
test
≤ 2.4 V
A
B
DA
Input
V
OC
B
A
Input
C
L
= 10 pF
(2 Places)
3 V
0 V
V
OC(PP)
V
OC(SS)
V
O
25 Ω, ±1% (2 Places)
D
D
Driver Enabled
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 3. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of V
OC(PP)
is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
7
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