Datasheet

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FEATURES

DESCRIPTION

GND

ATX/RX

A1A

A2A

A3A

A4A

BTX/RX

B1A

B2A

B3A

B4A

GND

C1A

C2A

C3A

C4A

CTX/RX

D1A

D2A

D3A

D4A

DTX/RX

GND

A1Y

A1Z

A2Y

A2Z

A3Y

A3Z

A4Y

A4Z

B1Y

B1Z

B2Y

B2Z

B3Y

B3Z

B4Y

B4Z

C1Y

C1Z

C2Y

C2Z

C3Y

C3Z

C4Y

C4Z

D1Y

D1Z

D2Y

D2Z

D3Y

D3Z

D4Y

D4Z

SN65LVDM1676DGG ( Marked as LVDM1676)

SN65LVDM1677DGG (Marked as LVDM1677)

(TOP VIEW)

SN65LVDM1676

SN65LVDM1677

SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVERS

• Sixteen Low-Voltage Differential Transceivers.

Designed for Signaling Rates up to 200 Mbps

per Receiver or 650 Mbps per Transmitter.

• Simplex (Point-to-Point) or Half-Duplex

(Multipoint) Interface

• Typical Differential Output Voltage of 340 mV

Into a 50- Ω Load

• Integrated 110- Ω Line Termination on

'LVDM1677 Product

• Propagation Delay Time:

– Driver: 2.5 ns Typ

– Receiver: 3 ns Typ

• Driver is High Impedance When Disabled or

With V

< 1.5 V for Power Up/Down

Glitch-Free Performance and Hot-Plugging

Events

• Bus-Terminal ESD Protection Exceeds 12 kV

• Low-Voltage TTL (LVTTL) Logic Input Levels

Are 5-V Tolerant

• Packaged in Thin Shrink Small-Outline

Package With 20 mil Terminal Pitch

The SN65LVDM1676 and SN65LVDM1677

(integrated termination) are sixteen differential line

transmitters or receivers (tranceivers) that use

low-voltage differential signaling (LVDS) to achieve

signaling rates up to 200 Mbps per transceiver

configured as a receiver and up to 650 Mbps per

transceiver configured as a transmitter. These

products are similar to TIA/EIA-644 standard

compliant devices (SN65LVDS) counterparts except

that the output current of the drivers are doubled.

This modification provides a minimum differential

output voltage magnitude of 247 mV into a 50- Ω load

and allows double-terminated lines and half-duplex

operation. The receivers detect a voltage difference

of 100 mV with up to 1 V of ground potential

difference between a transmitter and receiver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVERS FEATURES • • • • • • • • • Sixteen Low-Voltage Differential Transceivers. Designed for Signaling Rates up to 200 Mbps per Receiver or 650 Mbps per Transmitter. Simplex (Point-to-Point) or Half-Duplex (Multipoint) Interface Typical Differential Output Voltage of 340 mV Into a 50-Ω Load Integrated 110-Ω Line Termination on 'LVDM1677 Product Propagation Delay Time: – Driver: 2.
PAGE 2
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω.
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SN65LVDM1676 SN65LVDM1677 www.ti.
PAGE 4
SN65LVDM1676 SN65LVDM1677 www.ti.
PAGE 5
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) RATING VCC Supply voltage range VI Input voltage range |VID| Differential input voltage magnitude, (SN65LVDM1677 only) IO Receiver output current PD Continuous power dissipation ESD (1) (2) (3) –0.5 V to 4 V Electrostatic discharge A, TX/RX –0.5 V to 6 V Y or Z –0.
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SN65LVDM1676 SN65LVDM1677 www.ti.
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SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DRIVER tPLH Propagation delay time, low-to-high-level output 1.3 2.5 3.6 tPHL Propagation delay time, high-to-low-level output 1.3 2.5 3.6 tr Differential output signal rise time 0.5 1.2 tf Differential output signal fall time 0.5 1.
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SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION IOY Y II IOZ Z VOD VOY VOC VI (VOY + VOZ)/2 VOZ Figure 1. Driver Voltage and Current Definitions 3.75 kΩ Y VOD Input Z RL 3.75 kΩ ± 0 V ≤ VTEST ≤ 2.4 V Figure 2.
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SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) 3V VCC/2 Input tpLH Y Input Z VOD 0V tpHL 100% 80% RL VOD(H) Output CL = 10 pF (2 Places) 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
PAGE 10
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) IIY IIZ (VIY + VIZ)/2 Y VID IO A Z VIY VIC VO VIZ Figure 6. Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES RESULTING COMMONMODE INPUT VOLTAGE VIY VIZ VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.
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SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 1.2 V Z 500 Ω A Y 10 pF VO ± VTEST TX/RX NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST Y 1V 3V VCC/2 0V TX/RX tpLZ tpZL 2.5 V VCC/2 A VOL + 0.5 V VOL 0V VTEST Y 1.
PAGE 12
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 VIC − Common-Mode Input Voltage − V VCC > 3.15 V VCC = 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|− Differential Input Voltage − V Figure 9. DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.
PAGE 13
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 5 VCC = 3.3 V TA = 25°C VOL − Low-Level Output Votlage − V VOH − High-Level Output Voltage − V VCC = 3.3 V TA = 25°C 3 2 1 0 4 3 2 1 0 0 −20 −40 −60 IOH − High-Level Output Current − mA −80 0 Figure 12.
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SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) DRIVER EYE PATTERN TEST CONDITIONS • • • • VCC = 3.6 V TA = 25°C (ambient temperature) All 16 channels switching simultaneously with NRZ data. Scope is triggered at the same frequency with pulse. Input signal level = 0 V to 3 V single ended.
PAGE 15
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) (a) representative Transceiver configured as Rx @ 200 Mbps (Ch1 = xyA) (b) representative Transceiver configured as Tx @ 650 Mbps (M1 = xyY-xyZ) NOTE: x represents transceiver group A, B, C, or D, and y represents transceiver 1, 2, 3, or 4. Figure 15.
PAGE 16
SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDM1676DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN65LVDM1677DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDM1676DGGR TSSOP DGG 64 2000 346.0 346.0 41.0 SN65LVDM1677DGGR TSSOP DGG 64 2000 346.0 346.0 41.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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